Principal Metrology Engineer - PIC Wafer Fab
NOKIA | |
United States, California, San Jose | |
6373 San Ignacio Avenue (Show on map) | |
Oct 27, 2026 | |
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Job Family Description Develop, qualify, and maintain metrology recipes for CD-SEM, profilometry, overlay, ellipsometry, and defect inspection tools. * Own and support metrology equipment performance, qualification, and continuous improvement. * Develop metrology sampling plans and inline monitoring strategies. * Analyze process and metrology data to characterize processes and improve process control. * Monitor SPC charts and investigate process excursions using RCCA methodologies. * Support wafer-level failure analysis, including FIB, EDX, and coordination of external analyses. * Troubleshoot process and equipment issues in collaboration with Operations and Engineering teams. * Create equipment specifications, procedures, and OCAP documentation. * Train operators and technicians on metrology tools and procedures. * Support new technology development, process qualifications, technology transfers, and production ramp activities. Qualifications * MS in Electrical Engineering, Materials Science, Physics, or a related field. * 10+ years of semiconductor wafer fabrication experience (7+ preferred). * Strong problem-solving, data analysis, and communication skills. * Experience with statistical process control (SPC), failure analysis, and process characterization. * Hands-on experience with CD-SEM, profilometers, ellipsometers, and defect inspection tools preferred. * Experience with MES systems is a plus. * Experience in III-V semiconductor technologies (InP or GaAs) is highly desirable. * Familiarity with photolithography, etch, deposition, and CVD processes preferred. Work Schedule Compressed work week: Monday-Wednesday and every other Thursday, 12-hour day or night shifts. | |
Oct 27, 2026