IC Package Integration Engineer

Our team isseekinga highly motivated IC Package Integration Engineer to lead IC package manufacturing integration, yield, quality, and supply continuity for next-generation AI compute platforms. This role sits at the intersection of package design, manufacturing process development, and supply chain integration, ensuring advanced semiconductor packages transition smoothly from engineering builds into high-volume production.

In this highly visible role, the engineer will collaborate closely with EE, SI/PI, thermal/mechanical, reliability, and package design teams to review package architectures,identifymanufacturability risks early, and ensure robust design-for-manufacturing implementation. This role does not ownend-to-end IC package design. However, strong hands-on experience in package and substrate design is critical to effectively assess design decisions,identifypotential design limitations, and ensure designs areoptimizedfor high-volume manufacturing. The ideal candidate can bridge design intent with manufacturing reality and proactively flag issues before theyimpactyield, reliability, or scalability.

The engineer willinterface withmaterial suppliers, substrate vendors, foundry partners, and OSAT assembly/test vendors, driving process capability, yield improvement, and scalable manufacturing.

• Lead SoC package integration and high-volume manufacturing readiness, including ownership of OSAT/Foundry manufacturing processes
• Partner with OSAT/Foundry vendors to bring advanced packaging solutions from concept through qualification into high-volume manufacturing, with ownership of process capability, yield, quality, and ramp execution
• Drive package-level yield improvement, failure analysis, and reliability investigations, resolving issues across OSAT, substrate, and material suppliers
• Interface with substrate manufacturers and laminate suppliers to ensure stack-up integrity, manufacturability, and yield stability
• Review IC package and substrate designs using EDA tools (e.g., Cadence Allegro Package Designer or equivalent),identifyingdesign-for-manufacturability risks and ensuring seamless transition into production
• Evaluate and provide feedback on substrate stack-ups, via architectures (including DCTV, TTV), routing density, and power delivery structures, ensuring alignment between design and manufacturing constraints
• Collaborate with design teams to define and enforce design-for-manufacturing (DFM) guidelines across package architecture and substrate layout

• Master's Degree in Engineering, or related field, or equivalent experience
• 7+ years of experience in semiconductor packaging (2D/2.5D/3D etc.) spanning manufacturing integration and exposure to package or substrate design
• Hands-on experience with IC package or substrate design concepts, including substrate layout and routing fundamentals, via architecture and stack-up considerations, familiarity with test vehicle structures such as DCTV, TTV, or similar and experience with EDA tools such as: Cadence Allegro Package Designer or related
• Strong understanding of advanced packaging technologies, including flip-chip BGA, high-density substrates, multi-die integration, and high-power packages
• Hands-on experience with OSAT assembly processes (die attach, underfill, lid attach, ball attach, warpage control)
• Understanding of substrate materials and laminate systems, including CCL, glass fiber, and copper foil interactions
• Experience driving high-volume manufacturing ramp, yield improvement, and failure analysis
• Strong problem-solving skills with a data-driven approach